Intel sees path back to leadership in chip process performance – .

Intel sees path back to leadership in chip process performance – .

For decades, Intel has relied heavily on its manufacturing prowess as a key advantage over its various competitors like AMD, which had its own chip foundry which it established in 2009 and which became Globalfoundries. Its network of factories has allowed Intel to keep control of both the design and manufacture of its chips and more easily keep everything Moore’s Law compliant, from the first ideas to the eventual launch of processors.

But as we’ve noted in recent years, that manufacturing armor has been tarnished, giving new life to a growing host of chipmaking competitors and foundries in a processor market that has shaken the reigns a bit. from Intel. Rivals like AMD and Arm were able to reach the process level of 7 nanometers before Intel and are considering 5 nanometers and foundries like Taiwan Semiconductor Manufacturing Corp are expanding their advanced manufacturing capabilities. Consolidation – such as Nvidia’s $ 40 billion bid to buy Arm and AMD’s $ 35 billion bid to acquire programmable logic maker Xilinx – could mean that Intel will have much larger competitors at face in the near future.

Meanwhile, the delay in launching some chips – most recently the upcoming Xeon SP “Sapphire Rapids” processor – has further fueled the question of whether Intel has lost its manufacturing momentum and should soon consider relying more on them. foundries to manufacture its processors and on the market.

It was this situation that led some industry watchers to be surprised in March when CEO Pat Gelsinger – the longtime Intel executive who returned earlier this year to lead the chipmaker after nearly a decade at VMware – instead doubled Intel’s future of manufacturing with the announcement of IDM 2.0, an acceleration of its integrated device manufacturing model that includes spending $ 20 billion to build two new factories in Arizona, making chip factories in the United States and Europe available to other processor suppliers as part of an expansion and formalization of its own foundry and using other third-party foundries to create some Intel products, such as graphics chipsets and communication chips.

Intel’s future of manufacturing made the news recently with reports that the company was in negotiations to buy Globalfoundries for $ 30 billion (Globalfoundries has denied the rumors). All of this comes amid a global semiconductor shortage and pressure from the Biden administration to expand chip manufacturing capabilities in the United States.

The chipmaker intends to regain its position as the world’s leading manufacturer. At its Intel Accelerated event on July 26, Gelsinger and Ann Kelleher, CEO of Technology Development, present a processing and packaging roadmap that they believe will lead Intel to address performance parity in 2024 with other leaders and clear leadership a year later. The idea is to take advantage of the technologies available today – such as the SuperFIN manufacturing process and the Foveros 3D integrated circuit – and to bring new innovations over the next three years to remain competitive now while aiming for the leadership position. on the road.

“We have achieved competitiveness earlier than leadership, real parity,” Sanjay Natarajan, senior vice president and co-general manager of Intel’s logical technology development unit, said at a press briefing. . “If you slice and dice, then there are elements of competitiveness here in different ways for different segments. In the meantime, what we have first of all is the ability to offer some sort of holistic solution, a lot of the capabilities that packaging technology allows, where we can mix and match the best of what we can. assembling with the best is out there and ultimately delivering a compelling product and package along the way. It is certainly not the case that everything is going to be elsewhere. There will be elements that are already quite convincing and competitive today. In fact, if you look at our 10 nanometer SuperFin products, they are competitive. It’s not just my opinion, but what we read from the outside tells us that we are making competitive products even today. I think at the product level, you’re going to continue to see a competitive landscape right away. I’m talking about process technology leadership in 2025. ”

This will be done through a number of new innovations and the adoption of advanced technologies, aided by a node number system to make it easier for users, analysts and journalists to follow the steps ahead, Natarajan said. . Currently, 10 nanometer SuperFin products are in high volume production.

The new naming of the nodes will also reflect the reality of what is happening in the industry, Kelleher said. It’s still based on the idea that smaller is better, she said, but “I think the industry would basically agree with us that nanometer measurement no longer measures anything on the transistor. Based on this, we, along with the industry, decided that we needed to evolve our node name. This is [the result of] a whole bunch of feedback we’ve received over the years in terms of naming and as part of that we’re putting together a lexicon to talk about our process nodes and setting up the framework for it to be. clear, consistent and meaningful. It allows our customers and industry to look at our process nodes and make decisions on our process nodes and make that much easier for everyone.

Intel will also continue to stay focused on the performance per watt metric.

“One of the key aspects of, when moving from node to node, was the improved performance per watt you get with each successive node and any successful development,” Kelleher said. “This is a key aspect of what we are looking at in our process roadmap to 2025.”

The company’s EnhancedSuperFin nodes will be called Intel 7. They are still based on FinFET technology, which was first introduced at 22 nanometers, but it offers 10-15% performance per watt improvements over SuperFin. . Intel 4 will be the new name for Intel’s 7 nanometer process, which will fully adopt EUV lithography to print the extremely small features using ultra-short wavelength light. It will include not only area improvements but also another 20% jump in performance per watt. It will be ready in the second half of next year for products to be shipped in 2023, including “Meteor Lake” chips for customers and “Granite Rapids” for the data center.

Intel 3 will be the last FinFET process and will begin manufacturing products in the second half of 2023, resulting in an 18% increase in performance per watt. It will include high-performance library area scaling and Intel will increase the use of the EUV, Natarajan said.

The name Intel 20A is a nod to the transition from nanometers to angstroms. The nodes will include a few key innovations, including PowerVia and RibbonFET. PowerVia is a rear power system that switches interconnects to provide power and ground from the top of the transistor to the bottom. This will allow power to be “supplied directly to the transistor without the need to pass through the interconnect battery which virtually eliminates a voltage drop at the transistor.” This is a very big and significant saving in terms of energy efficiency, and it frees up all the top wires for signal routing. This will give us the option of either doing denser signal routing on the top, or making faster wires on the top and reducing resistance and capacitance between the lines.

RibbonFET, which is Intel’s implementation of an all-around transistor, will be the vendor’s first new transistor architecture since FinFET in 2011. It will be released with Intel 20A, which is expected to ramp up in the first half of 2024 and give Parity of Intel leadership in the industry. RibbonFET will feature multiple fins in a smaller area, providing faster transistor switching speeds with the same drive current.

After 20A comes 18A, which is under development and targeted for 2025. It will include more improvements to RibbonFET that will improve the performance of transistors. Intel is also working on the next-generation Large Numerical Aperture (NA) UVU, the next step in the UVR. Intel is working with ASML on the development of High NA EUV.

The packaging will also be the key. Intel has been using EMIB (Integrated Multi-Die Interconnect Bridge) in its products since 2017, believing that Sapphire Rapids will be the first Xeon chip to ship in volume with EMIB. After Sapphire Rapids, the next generation of EMIB will go from a bump pitch of 55 microns to 45 microns. Meanwhile, Meteor Lake will mark the second-generation use of Foveros – a wafer-level packaging technology introduced in 2019 with Intel’s “Lakefield” hybrid processors – in a customer product. It will feature a 36 micron hump pitch, slabs spanning multiple tech nodes, and a thermal design range of 5 watts to 125 watts.

In 2023, Intel will deploy Foveros Omni and Foveros Direct. Foveros Omni will offer great flexibility through 3D stacking technology which will result in matrix-to-matrix interconnection and modular design. It will also allow multiple tiles from top matrices and base tiles to be mixed, giving Intel “a tremendous ability to mix and match our different styles together and create products that people weren’t able to look at before,” said Babak Sabi, corporate vice president and general manager of assembly and test development at Intel.

Foveros Direct, which will be complementary to Foveros Omni, will provide low resistance interconnects with a direct copper-to-copper link. It also blurs the line between the end of the wafer and the start of the case and allows for bump pitches of less than 10 microns which will increase the interconnect density for 3D stacking. This will lead to new developments in the functional division of matrices.


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