Apple’s new 5G iPhones, which it is expected to unveil tomorrow, introduce an important new technology term. Not 5G, available from other companies for over a year. Instead, the phone contains the world’s first processor built from 5 nanometer (nm) transistors: the A14. (The chip also appears in the upcoming iPad Air 4.) Over the next year, these tiny transistors will appear in high-tech PCs, servers, and smartphones from many vendors.
For decades, smaller transistors have enabled all kinds of impressive technological advancements. At a relentless pace known as Moore’s Law, transistor shrinkages have allowed chipmakers to pack more cores and new capacity into their chips while maintaining or even reducing costs and power. Among other things, Moore’s Law was a key factor in the transition from bulky phones that could barely send text messages to the sleek supercomputers we pocket today.
But recently this trend collapsed as the size of the transistor nears natural limits: 5nm is the size of 10 large atoms. Building something so small, billions at a time, requires new and extremely expensive equipment. After spending money on the manufacturing problem, chipmakers also face limits on how fast data moves on the chip and how much power is needed to move it. As a result, the new 5nm technology offers little benefit in terms of cost or speed. This shortfall will make it difficult for chipmakers to make significant performance gains.
Build small transistors
Chip factories, or fabs, shine bright light through a “mask” that creates lines and shadows on the chip, scorching the surface except in the shadows. At 5nm, however, some of the lines are smaller than the wavelength of visible light. Thus, the industry is shifting to a new approach that uses extreme ultraviolet light (EUV), which is similar to x-rays. It is difficult to simply generate EUV light, which requires a laser beam that transforms the droplets of. bright plasma tin. Building mirrors, lenses, and masks for those nearby x-rays is another tall order.
Only one company in the world (ASML in the Netherlands) can produce EUV manufacturing equipment; just one of these machines weighs 180 tons and costs up to $ 120 million, and a high-tech factory needs several. So, the cost of a single EUV layer on a chip is about three times the cost of a layer that uses traditional processing. The previous generation 7nm technology requires the UVV for only four layers, but 5nm requires 10 to 12 EUV layers. These cost increases negate most of the benefits of smaller transistors; While Moore’s Law has historically reduced the cost of transistors by 40%, the benefit of 5nm is likely to be only 10%.
The smaller transistors are also faster, but that doesn’t help the latest processors. Think of a transistor as a traffic cop at an intersection ordering red cars to go right and blue cars to turn left. If the intersection is 10 lanes wide, it will take longer for the cop to cross the lanes and steer cars. As the intersection gets smaller, the cop can stand still and point fingers. In this way, smaller transistors can change data faster.
The problem is that the roads are also getting smaller. Chips use wires that must shrink at the same rate as the transistors they connect. Like a two-lane road that replaces a highway, the thinner wires become a bottleneck. Some factories introduce cobalt instead of copper for interconnects, but this new material adds additional cost and complexity to the manufacturing process.
These problems will worsen in the future. The next-generation 3nm transistors, which are slated to start shipping in 2023, will require even more EUV layers and other new features that increase the cost. As a result, Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) spent $ 10 billion to build its 5nm plant and budgeted $ 20 billion for its 3nm plant; these increases make it difficult to reduce the cost of the chips. Compressing the data over even tighter connections could negate any improvement in transistor speed.
What comes after the end?
Moore’s Law continues to provide smaller transistors, with Apple’s 5nm processor leading the way. But the clock speed gains in this generation are only around 10%, and the cost improvement is also modest. In one or two more generations, these gains will likely disappear entirely. Even if factories can find a way to build smaller transistors, their heroic efforts will eventually become too expensive for their customers.
For companies like AMD, Intel, and Nvidia, the way forward will require improving chip design rather than simply relying on faster, cheaper transistors. Faster chips will need to be optimized for their customer’s workloads, delivering new designs that can speed up specific software. To deliver such designs, chip designers must have a thorough understanding of the end application of their products. Just cranking the crank on a versatile design won’t be enough.
This emerging environment will reward daring companies that are ready to try new architectures and techniques. Successful businesses must also pay close attention to the needs of CIOs and other customers. Nvidia exemplifies this approach best, adding new features to its chips to speed up specific AI workloads as well as ray tracing for PC games. To better understand its customers’ challenges, the company uses its own chips to build systems and even an entire data center.
The good news for CIOs is that processor vendors now offer application-specific solutions to meet their needs. The challenge is to assess these platforms; it is no longer sufficient to check the number of cores and the clock speed to determine performance. Practice tests of specific software will help separate advanced designs from those still waiting for Moore’s Law to register them.
Disclosure: The Linley Group, a research services provider, receives revenue from most of the tech companies named in this article.