Both SKUs will have a large “Sunny Cove” processor core, as well as four small “Tremont” Atom processor cores. Both sets of cores will have access to the latest 4MB cache, though Intel has yet to reveal what type of cache it is.
Meanwhile, Intel is integrating a Gen11 GPU with 64 threads, the same number of UEs as on Intel’s Ice Lake processors. Interestingly, the iGPU is clocked at roughly half the usual value for an Intel GPU, with clock speeds as low as 500 MHz – suggesting that Intel is going wide and slow to boost graphics performance. The two processors will be evaluated for a TDP of 7 W.
|Intel Lakefield processors|
|i5-L16G7||1 + 4||1400||3000||1800||64 EU||500||4267||7 W|
|i3-L13G4||1 + 4||800||2800||1300||48 EU||500||4267||7 W|
Intel has confirmed to us that the base frequency is the unified frequency across the five cores, and the single-core turbo frequency applies only to the large core of Sunny Cove. Support for LPDDR4X-4266 is a step up from the memory controller in Ice Lake, which only works on LPDDR4X-3733, and memory speed will likely increase performance.
In order to activate these processors in a small 12mm x 12mm footprint, Intel uses its 3D stacking technology, called Foveros. This means that the logical areas of the chip, such as cores and graphics, lie on a 10+ nm chip, while the IO parts of the chip lie on a 22 nm silicon chip and are stacked together. In order to make the connections work, Intel has activated 50 micron connection pads between the two silicon halves, as well as power-oriented TSVs (via silicon vias) to power the cores on the upper layer.
Intel lists the TDP for these 7 W chips, although the company has not disclosed turbo power limits for the chip. As mentioned above, Intel has not disclosed how the cache works. In the initial diagrams, we were shown that PoP memory would be added at the top, and although Intel did not provide more details there, we know that last month’s Samsung Galaxy Book S reveals that it there will be (at least) 8 SKU SKUs using LPDDR4X.
We have big questions about how each of the cores will work, since by default they support different instruction sets – Intel hasn’t provided any information on this yet. Intel has stated that the planning of the threads on the different parts of the CPU will be done on the basis of a hardware-guided operating system planning, although Intel has not gone into the details of its hardware tracking and activating the way this is done. In the demos we’ve seen, Lakefield will use Tremont cores for almost everything, and will only use the heart of Sunny Cove for user experience interactions, such as typing or interacting with the screen.
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Intel is planning a post-announcement briefing so the press can ask questions, which means that the announcement is in two parts. This is the information given to us in advance, and we will update you with the details of the post-announcement briefing. As part of this process, we exclaimed at Intel how frustrating this way of presenting details to the press – first for readers, as you will all have to come back if you want to find out what Intel is telling us later in the day. , but secondly for us, as the press, who will have to scramble to jump into the details and decide whether to write quickly and miss details, or write slowly and miss the traffic wave.
One thing we can confirm in advance – the Sunny Cove does not appear to be AVX-512 compatible. Intel’s initial press release says that AI workloads are happening on the processor; given the additional power consumption required for AVX-512, this is probably a good thing.
More information on the Intel post-announcement media availability will arrive later today.